1. Field of the Invention
The present invention relates to a substrate frame for connecting to external terminals the electrodes of semiconductor chips mounted on the substrate frame and a method of making semiconductor devices using the substrate frame.
2. Description of the Related Art
Japanese patent application Kokai No. 11-87386 discloses such a semiconductor device as shown in FIGS. 2(a) and 2(b), wherein a semiconductor chip 2 is mounted on the first surface of a wiring substrate 1 with a conductive or insulative adhesive 3, with the circuit forming surface facing up. A plurality of pads or connecting electrodes 1a and their wirings (not shown) are formed on the first surface of the wiring substrate 1. The pads 1a are exposed but the wirings and the other area are covered by a solder resist. A plurality of wires 4 connect the pads 1a and the pads 2a of the semiconductor chip 2. The semiconductor chip 2, the adhesive 3, and the wires 4 are covered by a resin such as epoxy resin.
A plurality of pads and their wirings are formed on the second surface opposed to the first surface of the wiring substrate 1. Similarly to the first surface, the pads are exposed but the wirings and the other area are covered by a solder resist. A plurality of external terminals or solder balls 6 are joined to the pads on the second surface. It is understood that the wirings on the first and second surfaces are connected via through-holes.
How to make such a semiconductor device will be described.
As shown in FIG. 2(c), a substrate frame 10 is prepared by bonding a pair of copper foils on opposite surfaces of an insulating board and forming a row of wiring substrate regions 11 at predetermined intervals on each surface. On each wiring substrate, both the surfaces are etched to form wiring patterns that include pads on the first and second surfaces of a wiring substrate 1 (FIG. 2(a)) and through holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces. A nickel-gold (NiAu) electrolytic plating is applied to the interiors of the through holes for connecting the wiring patters and to the pads for increasing the bonding property with the wires 4 and the solder balls 6. A solder resist is applied to the wiring patterns and the other area but the pads.
A plurality of slits 12 are provided between the wiring substrate regions 11 and have a length less than that of the wiring substrate regions 11. A plurality of slits 14 are provided in the ear portions 13 of the substrate frame 10 and have a length less that that of the wiring substrate regions 11. These slits 12 and 14 are formed by a router process. A semiconductor chip 2 is bonded to a central mounting area 11a of the wiring substrate region 11 with a bond 3. Then, the pads 1a of the wiring substrate region 11 and the pads 2a of the semiconductor chip 2 are connected with wires 4. Then, the semiconductor chip 2, the bond 3, and the wires 4 within a package area 11b are enclosed with a resinous mass 5. A plurality of solder balls 6 are joined to the pads on the second surface of the wiring substrate region 11. Finally, the ear portions at the four corners of the wiring substrate region 11 are punched off to provide individual semiconductor devices.
However, the conventional semiconductor device suffers from the following disadvantages.
A pair of lead patters are formed between the wiring substrate region 11 and the ear portion 13 of the substrate frame 10 for electroplating the wiring pattern. The punching at the four corners of the wiring substrate region 11 can damage the cut face, lowering the reliability. The punching may be replaced by cutting the four corners with a rotary saw. The saw cutting, however, requires cutting in the vertical and lateral directions, lowering the productivity, especially, of large BGA.